1. Field of the Invention
The present invention relates to a delay device and a delay time measurement device, each of which employs a ring oscillator, and further relates to an exclusive-OR circuit for use in the delay device.
2. Description of the Related Art
For improved operating rates of components such as an LSI, etc., a delay circuit for dynamically adjusting a phase lag between an internal clock signal of the LSI and an external clock signal is required. To match the timings of the internal clock signal and the external clock signal more precisely, a minimum step of delay that the delay circuit can generate must be improved.
FIG. 1 shows a structure of a conventional delay circuit. This delay circuit comprises a plurality of serially connected buffers 11, and a selector 12 for selecting and outputting one of signals output from the plurality of buffers 11. The selector 12, which is supplied with a delay predetermining digital value for predetermining an amount of delay time from an input signal, outputs a signal according to the delay predetermining digital value. As a result, the selector 12 outputs the signal with a delay time of a predetermined digital value.
Additionally, the above described delay circuit employs an exclusive-OR circuit shown in FIG. 2, to output an inverted signal and a non-inverted signal of an input signal.
In this exclusive-OR circuit, the input signal is input to one of the control terminals of transfer gates 23 and 24 unchanged, and it is input to the other of the control terminals via an inverter 21. In addition, an inversion control signal is input to the transfer gate 23, and a signal generated by inverting the inversion control signal by the inverter 22 is input to the transfer gate 24.
To make the minimum step of delay smaller without affecting the maximum delay in the above described conventional delay circuit, it is required to reduce the amount of delay of one buffer, and to increase the number of serially connected buffers, which leads to a larger scale of buffer circuitry. As the number of buffers increases, the scale of the selector circuitry becomes larger. As a result, the scale of the whole delay circuit also becomes larger.
For the above described exclusive-OR circuit, there is a difference between the load when outputting an input signal with inversion and when outputting the input signal without inversion, as viewed from the side of outputting an inversion control signal. Accordingly, the amount of delay time may vary depending on whether or not to invert the input signal to be output.